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ZIPCPU及相关的设计资源

元器件信息 2022-12-02 16:15 398 0

官方网址
Github上的资源
关于ZIPCPU
- 由Gisselquist Technology, LLC.公司开发的运行在FPGA上的开源、全功能软核CPU
- 32位CPU - 所有的寄存器都是32位宽、地址也是32位，指令也是32位
- RISC架构
- Load/Store架构
- 兼容Wishbone，所有外设都通过存储器映射的I/O来寻址
- 冯诺伊曼结构：指令和数据共享总线
- 流水线结构
- 可以根据逻辑资源进行配置的CPU
- 可以用于各个厂商的FPGA
采用的工具
- SymbiYosys
关于入门FPGA/Verilog的课程（PDF文件）
- 前言
- Wires和组合逻辑
  - Thruwire example code
  - Maskbus example code
- 寄存器以及点灯
  - Blinky example code
  - PPS-I and PPS-II example code
  - Dimmer example code
- 有限状态机
  - LED Walker example
- 构建一个Wishbone从设备
  - LED Walking upon request example
- 用串口发送创建一个Hello Word
  - Hello world
- 用串口发送32位数据
  - TX-data
- 按键：2FF同步以及消抖
  - Bouncing
- 使用FPGA的块RAM
  - Memory-TX
- 构建一个串口接收器
  - UARTRX
- 位串口构建一个FIFO
  - FIFO
参考项目
- The ZipCPU
  - A Quick Introduction to the ZipCPU's Instruction Set
  - Instructions for building the GCC-based toolchain
  - data cache
  - MMU
  - AutoFPGA
    - An FPGA Design Automation routine
    - A Brief Introduction to AutoFPGA
- 移植在FPGA上的ZipCPU
  - S6SoC
  - ArrowZip
    - 使用MAX1000开发板
    - 文章：Arrow's Max-1000: A gem for all the wrong reasons
  - OpenArty
  - XuLA2-LX25SoC
- ZBasic
- VideoZIP
- ICOZip
- DSP相关的Cores
  - CORDIC
    - table based sinewave generator
    - quarter-wave table based sinewave generator
    - CORDIC based sin/cosine generator
    - quadratically interpolated sinewave generator
    - CORDIC based arctangent
    - 文章 - 关于数控振荡器
    - 文章 - 在FPGA里用最简单的方法产生正弦波
  - DSP Filters
  - Interpolation
    - nearest neighbor
    - linear
    - quadratic
  - Double Clock FFT
  - FFT Demo
  - PLLs
    - logic PLL
- 与CPU外设相关的Cores
  - QSPI flash controller
    - SPI flash core
    - Dual SPI flash core
    - 文章 - 如何用FPGA构建一个SPI Flash控制器
  - Wishbone based scope
  - SD-card controller
  - block RAM controller
  - Hyper-RAM Controller
  - RMII Ethernet Controller
  - Ethernet Packet controller
  - I2C Controller
  - Real-Time Clock
  - Real-Time Date
  - Organic LED controller
  - GPS controlled clock
  - PWM Audio Controller
  - 文章 - 重新发明PWM
  - 文章 - 演示改进的PWM波形
  - VGA controller
  - UART
    - TX
    - RX
    - 同步FIFO
  - Wishbone DDR3 SDRAM Controller
- WB FM transmitter hack
技术文章
- FPGA设计新手的规则
- 如果调试FPGA？
  - blinky
- 什么是仿真？
- Vision for controlling (and debugging) an FPGA
- Getting that first UART working
  - Using Sequence Properties to Verify a Serial Port Transmitter
- Debugging by simple bus address
- how to debug an FFT
  - how I formally verified the FFT itself
  - debug an AXI Streams
- 调试控制接口
  - overview of an example UART-wishbone bridge
  - build command words for our debuging wishbone interface
  - simple wishbone bus master
  - turn responses from the wishbone bus into an output serial stream
  - interrupt support
  - Adding a debug port idle indicator
  - Connecting stream components together
  - simple wishbone interconnect
  - set up a test bench
  - outline of how the software controller will work
  - How to build a software controller
  - get started with a wishbone scope
- 开源FPGA设计工具
  - Looking at Verilator
  - yosys-smtbmc, and the formal methods it allows
  - Makefiles for formal proofs with SymbiYosys
  - Using an open source VGA simulator
  - Just how long does a formal proof take to finish
  - Is formal verification enough, or is simulation required
- FPGA设计基础
  - real FPGA design process
  - It cannot be done
  - Knight Rider LEDs
  - Generating Timing
  - Minimizing LUTs
  - Strategies for Pipelining logic within an FPGA
  - Project Ideas: the PMod AMP2
  - Handling clock domain crossings
    - Formally verifying the synchronizer for an asynchronous reset
    - Using a FIFO to pass data from one clock domain to another
  - Reasons why Synthesis might not match Simulation
  - Rules for new FPGA designers
  - Breaking all the rules to create an arbitrary clock signal
  - Lessons in Hardware Reuse
- 如何构建和调试一个软核的CPU
  - Building and formally verifying a general purpose ultra-micro controller
  - How to debug a CPU core for an FPGA
    - Which came first: the CPU or the peripherals?
    - Thinking about the debug capabilities you will need, before you build
    - Debugging your CPU using Verilator
    - The structure of a simple ALU
    - The first ZipCPU prefetch
    - How the ZipCPU handles its pipeline logic
    - Mystery post: The ugliest bug I’ve ever encountered
    - Updating ZipCPU files
    - Building the ZipCPU toolchain, and demonstrating its pipeline
      - Besides building the toolchain, this post offers a fun way to view how the logic moves its way through the ZipCPU as a result of the three separate ZipCPU prefetch modules.
    - Building and using an example ZipCPU demonstration design: ZBasic
      - This discussion also includes a demonstration of what it takes to run 4x4x4 Tic-Tac-Toe on the ZBasic architecture.
    - Debugging your CPU while on the FPGA
      - Here, we discuss how the ZipCPU can be halted, stepped, and even reset from the debugging bus.
    - Building a compromise prefetch module – one that isn’t as light on logic as the basic prefetch, but yet offers more performance than the prefetch and cache module.
    - The ZipCPU’s interrupt controller
    - Profiling your CPU using Verilator
      - This will be about how I was able to measure, and optimize, every clock used by my CPU (as implemented on the XuLA2-LX25 when running the Dhrystone benchmark.
    - Building a better Verilog Multiply for the ZipCPU
  - How to debug the ZipCPU when running the ZipOS found on the S6SoC
  - o How a really simple Operating System works.
    - Why does blinky make a CPU appear to be so slow?
    - The ZipCPU meet blinky discussing how to run blinky across multiple threads
- Wishbone总线
- AXI总线
- 互联
- SoC + FPGA架构
  - How to interact with an FPGA from a CPU
- CPU设计话题
  - An overview of the ZipCPU instruction set
  - How to build a back-end for GCC and/or binutils
  - Debugging a CPU
  - Putting the pieces together to build a data recorder
  - How to build a back-end for your soft-core using GDB
- DSP话题
  - Quantization error analysis
  - Representing angles within an FPGA
  - Debugging DSP algorithms
  - A basic histogram implementation, and then what happened when I went to use it
  - Interpolation
    - o Nearest Neighbour
    - o Series: How to build a Linear Interpolator
    - o Interpolation is just convolution
    - o Quadratic interpolator
    - o A filter based upsampling interpolation method
    - o Polynomial Interpolation a.la Harris
    - o Why splines are entirely inappropriate for real-time DSP
  - CIC Filters
  - o CIC upsampler
  - o CIC downsampler
  - Sine, Cosine, and Arctangent calculation
    - o Table based sin/cos generation
    - o Quarter wave table based sin/cos generation
    - o What is a CORDIC, and how do I use it?
      - Generating Sin/Cos using a CORDIC
      - Using a CORDIC as a phase measuring device
      - The basic CORDIC test-bench
      - Basic logic design of a numerically controlled oscillator
      - Downconverting an incoming signal using a CORDIC
      - Generating AM, FM, and QAM types of signals using the CORDIC
    - o A quadratic table based sin/cos generator, optimized for reduced phase noise and reduced spur energy. This requires two multiplies, and so it improves performance over the CORDIC approach
  - 关于数字滤波器的一些通用话题
    - o High speed filtering. These filters will run at your system clock speed, or not at all.
      - A pair of very simple digital filters
      - The Moving average filter
      - High speed FIR implementation
        An improved high-speed implementation
      - High speed symmetric FIR implementation
      - Halfband FIR implementation
      - Hilbert Transform
    - o Low-speed filtering. These filters run N times slower than your system clock speed. They are more efficient, if you can use them.
      - In general, these will be the same filters as their high speed counterparts.
      - A Generic (slow) FIR filter.
      - A cascaded slow FIR filter. This article will present an approach that allows you to cascade filter blocks together in order to implement a longer filter.
      - A symmetric slow FIR filter. This article modifies the generic (slow) FIR filter, in order to optimize it to exploit the linear phase relationship within it. This article goes through the background of why a symmetric filter is, as well as why such an implementation is superior to the generic one.
    - o Building a delay
    - o Estimating a filter’s cost
  - 多数率信号处理
    - o Implementing a downsampler and filter
  - How to test a digital filter
    - o Improved PWM: How to generating a cheap audio signal from an I/O pin
    - o Testing the improved PWM signal
    - o Building a generic filtering test harness
      - Evaluating the filter’s frequency response
      - Testing a generic filter using the test harness
    - o Finding IIR limit cycles
  - Generating a pseudorandom noise sequence
    - o An Exampe LFSR
    - o Getting many bits per clock from an LFSR
  - Digital PLL design
    - o A logic PLL, running at the system clock rate
    - o Adjusting our logic PLL to handle I+Q
    - o PLLs with better (CORDIC-based) phase estimators
    - o Using a PLL together with a FIFO, for asynchronous sample rate conversion
  - FFT and other spectral estimation topics
    - o Cheap spectral estimation
    - o An Open Source Pipelined FFT
    - o Implementing a pre-FFT window function
    - o Building a scrolling raster framebuffer
    - o Color mapping the FFT’s results to the framebuffer
    - o Maximally resolved FFT window functions
    - o Optimizing the window function for high spectral resolution
  - Discrete Fourier Transform Filter Banks. (Teaser)

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