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Controlpaths.com上与Xilinx FPGA、SoC以及数字信号处理相关的技术文章

元器件信息 2022-12-02 16:14 253 0

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硬件
- Ripple suppression circuit for PWM DAC.
- Getting started with Microchip’s FPGA Icicle Kit and PolarFire SoC.
- Discovering Gowin FPGA.
- FFT algorithm using an FPGA and XDMA.
- Controlling a SMPS from MSS with SmartFusion2 SoC.
- Creating Pynq images for custom boards.
- Development boards I use.
- Connecting an SSD to Zynq MPSOC.
- Discovering SDR with GNU Radio and USRP B205Mini.
- Designing an FPGA board.
- Genesys ZU and Zynq US+.
编程
- Building a SoC with Litex.
- Implementing a dual core processor in FPGA.
- Using PCIe in Xilinx 7 Series.
- Creating a RISC-V based design on SmartFusion®2 SoC
- Discovering the SmartFusion® 2 SoC.
- Using IIO to manage an ADC from Petalinux.
- Using HDL Coder WFA to implement a distortion effect.
- Using FPGA Data Capture to debug a design.
- Using DSP48E1 Slice.
- Increasing ADC resolution using oversampling.
- Using Xilinx’s FIR Compiler.
- Creating an AXI Stream IP for an acquisition system.
- Using the DMA and AXI4 Stream on Zynq US+.
- Asymmetric multiprocessing on Zynq MPSOC.
- Custom AXI IP for acceleration.
- Emulating hardware with Zynq.
- Real time filter compute with Pynq.
- DDR resources.
- Why I use scripting?
数字信号处理
- Single pole filter without multiplications.
- Designing a filter on MATLAB and verifying it using FPGA-in-the-loop and Eclypse Z7
- Implementing high order filters with FIR Compiler.
- Equalizing IIR filters for a constant group delay.
- Audio equalizer based on FIR filters.
- Adding windows to xFFT IP.
- Implementing a FIR filter using folding.
- Implementing a digital biquad filter in Verilog.
- Managing AXI4-Stream from MATLAB.
- Using MATLAB and FPGA-in-the-Loop to design a filter (Part 2)
- Using MATLAB and FPGA-in-the-Loop to design a filter. (Part 1)
- Using moving average filters for hard filtering.
- Single tone detector with Genesys ZU and RTU.
- EclypseZ7, Petalinux and signal processing at the edge.
- Eclypse Z7 and xFFT.
- Eclypse Z7, ZMODs and SYZYGY.
设计流程
- Why FPGA?
- Remote debugging via hardware server.

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